FIG. 1 is a block diagram illustrating an example of a circuit simulation workflow. Generally, a circuit designer may use a hardware description language (HDL) (e.g., Verilog) to describe or code a circuit through equations and behavior descriptions. The HDL is then synthesized into a netlist 110 from a library. The netlist's library elements have detailed descriptions in the form of transistor level subcircuits. The netlist 110, together with the library subcircuits, input waveforms 115 and the boundary conditions 120, may be simulated and verified using a circuit simulation program (e.g., SPICE (simulation program with integrated circuit emphasis)), as shown in block 105. The output 125 of the circuit simulation program 105 may be used to generate a statically pre-characterized model. Current circuit simulation technologies are not adapted to handle large circuits efficiently.